Many semiconductor modules use Controlled Collapse Chip Connection (C4) solder balls or bumps to connect the circuitry side of the chip to the substrate. Chips using C4 technology are commonly referred to as either "C4 chips" or "flip chips." For flip chips designed to be wire bonded to a substrate, the C4 pattern is typically around the perimeter of the chip. For flip chips requiring greater numbers of interconnections, and that have been designed for C4 connections, a fully or partially populated array of C4 connections is used. In modules that are not hermetic, and that use C4 connections, an epoxy underfill is typically used. The underfill serves two purposes: (1) it provides environmental protection of the chip circuitry and the solder connections, and (2) it carries some of the shear loading between the chip and the carrier, thus extending the fatigue resistance of the C4 connections.
For example, FIG. 1 shows a conventional semiconductor module assembly 8 comprising flip chip 10. Flip chip 10 is mounted to substrate 14 using C4 solder balls 12. This mounting is usually accomplished by use of an automated placement tool. A thin layer of flux (not shown) is usually applied to either the top surface of substrate 14 or to solder balls 12. After placement of flip chip 10 on substrate 14, the assembly is typically run through a reflow furnace in which oxygen levels are controlled to very low levels. The C4 solder balls 12 are typically a lead-tin alloy, such as 97% lead and 3% tin or 37% lead and 63% tin (by weight). Substrate 14 is typically ceramic, but can be an organic substrate, or may comprise any substrate materials known in the art. Substrate 14 has input-output connections 18 such as Pin Grid Array (PGA), Ball Grid Array (BGA), Column Grid Array (CGA), or Land Grid Array (LGA) connections.
Although the array of C4 solder balls 12 is typically well-aligned to a corresponding array of solder-wettable pads (not shown) on the top surface of substrate 14 by the placement tool, the surface tension of the reflowed solder balls automatically re-aligns the two arrays during the solder reflow step. During cooling, C4 solder balls 12 solidify and rigidly attach flip chip 10 to substrate 14. Such attachment provides both a mechanical and an electrical connection between the flip chip 10 and the substrate 14.
Underfill 16 is typically applied to preheated module assembly 8 by an automated dispense tool (not shown). The module assembly 8 is typically preheated to effectively reduce the viscosity of underfill 16, thereby reducing the time required for and improving the effectiveness of the underfill process. Underfill 16 is typically applied along a single edge of flip chip 10 and then allowed to flow by capillary action to completely fill the spaces between flip chip 10 and substrate 14, thus surrounding C4 solder balls 12.
Depending on the size of flip chip 10 and the viscosity of underfill 16, a single dispense pass may be sufficient. Multiple passes may be required, however, with sufficient delay allowed between each pass to allow the underfill 16 to completely flow under the flip chip 10. Generally, the presence of a fillet 13 of underfill 16 around the complete perimeter of flip chip 10 indicates that enough underfill 16 has been applied. Then, the underfill 16 is cured by any of several mechanisms known in the art, such as exposure to heat, ultraviolet light, or microwave energy.
Although it is not uncommon for wirebond chips to be mounted in cavities, flip chips have typically been joined to substrates without a need for cavities. In a recent effort to bring the function of separate chips as close together as possible on a package, some modules have been designed with a large chip attached using C4 technology to both a substrate and to a smaller chip. Referring now to FIG. 2, there is shown a module assembly 19 comprising a larger chip 20 with a smaller chip 22 attached to the larger chip 20. The stacked chip structure 23 is joined to a substrate 14'.
The C4 solder balls 12 around the perimeter of larger chip 20 are attached to substrate 14'; the C4 solder balls 12' near the middle of the larger chip 20 are attached to smaller chip 22. Solder balls 12 and 12' may comprise the same alloy, or solder balls 12' between chips 20 and 22 may be of a higher melting temperature alloy than solder balls 12 between larger chip 20 and substrate 14' so that solder balls 12' do not reflow when larger chip 20 is joined to substrate 14'. To prevent interference between smaller chip 22 and substrate 14', there is a shallow cavity 24 in the substrate 14' that can accommodate the smaller chip 22.
The configuration of stacked chip structure 23 within cavity 24 presents some difficulties, however, in providing underfill (not shown) by conventional underfill techniques. Although underfill applied along the edge of larger chip 20 flows under larger chip 20 and is drawn under and around the perimeter of larger chip 20 by capillary action, capillary action is insufficient to draw underfill into cavity 24 or into the space 25 between chips 20 and 22. Thus, although the underfill may fill the thin gaps 26 between larger chip 20 and substrate 14', it does not provide the desired coverage in cavity 24 or spaces 25. As a result, air trapped in those regions may compromise the integrity of module assembly 19 if the trapped air expands during subsequent heating steps typically used to cure the underfill.
U.S. Pat. No. 5,760,478 issued to Bozso et al. describes a system comprising two flip chips connected face-to-face by conventional solder connections, with one or both of the chips having a chip-to-substrate connection for power and signal. For instance, a low-power device, such as a Dynamic Random Access Memory (DRAM) chip, may be attached directly to a higher-power logic chip, with the logic chip also connected to a substrate. In the preferred embodiment, both the chip-to-chip connections and the chip-to-substrate connections are solder connections. The low-power chip is smaller than the higher-power chip and fits under the larger chip within a cavity in the substrate, as is shown in FIG. 2 by Bozso et al. This type of structure presents difficulties in providing underfill by conventional techniques, as described above.
Thus, there is a need in the art for a process and module structure that enables underfill of such stacked chip structures while avoiding the problems of the prior art.